The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2009
Filed:
Dec. 18, 2007
Wei Han, Beaverton, OR (US);
Yoshita Yerramilli, Folsom, CA (US);
Loren Mclaury, Hillsboro, OR (US);
Warren Juenemann, Cornelius, OR (US);
Wei Han, Beaverton, OR (US);
Yoshita Yerramilli, Folsom, CA (US);
Loren McLaury, Hillsboro, OR (US);
Warren Juenemann, Cornelius, OR (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
Various techniques are described to test memory arrays of a programmable logic device (PLD). In one example, a PLD includes a first memory array. The PLD also includes a plurality of sense amplifiers adapted to read a plurality of data values stored by the first memory array and provide a plurality of data signals corresponding to the data values. The PLD further includes a test circuit adapted to test the first memory array. The test circuit is coupled with the sense amplifiers and adapted to compare the data signals with a test signal to provide a pass/fail signal. In addition, the PLD includes a second memory array. The PLD also includes a data shift register adapted to test the second memory array.