The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7629253 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 08, 2009

Filed:

Mar. 30, 2007
Applicant:

Yoichiro Tanaka, Santa Clara, CA (US);

Inventor:

Yoichiro Tanaka, Santa Clara, CA (US);

Assignee:

Sandisk 3D LLC, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.


Find Patent Forward Citations

Tanaka, Yoichiro. (2009). Method for implementing diffusion barrier in 3d memory (U.S. Patent No. 7629253). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7629253

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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