The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2009

Filed:

May. 29, 2008
Applicants:

Soo-ho Shin, Yongin-si, KR;

Sun-hoo Park, Yongin-si, KR;

Byung-hyug Roh, Yongin-si, KR;

Young-woong Son, Hwaseong-si, KR;

Sang-wook Lee, Seoul, KR;

Inventors:

Soo-Ho Shin, Yongin-si, KR;

Sun-Hoo Park, Yongin-si, KR;

Byung-Hyug Roh, Yongin-si, KR;

Young-Woong Son, Hwaseong-si, KR;

Sang-Wook Lee, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 31/062 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes first gate structures, second gate structures, a first capping layer pattern, a second capping layer pattern, first spacers, second spacers, third spacers, and a substrate having first impurity regions and second impurity regions. The first gate structures are arranged on the substrate at a first pitch. The second gate structures are arranged on the substrate at a second pitch greater than the first pitch. The first capping layer pattern has segments extending along side faces of the first gate structures and segments extending along the substrate. The second capping layer pattern has segments extending along the second gate structures and segments extending along the substrate. The first spacers and the second spacers are stacked on the second capping layer pattern. The third spacers are formed on the first capping layer pattern.


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