The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2009

Filed:

Oct. 31, 2006
Applicants:

Charles J. Alpert, Cedar Park, TX (US);

David J. Hathaway, Underhill, VT (US);

William R. Migatz, Wappingers Falls, NY (US);

Gi-joon Nam, Austin, TX (US);

Haoxing Ren, Austin, TX (US);

Paul G. Villarrubia, Austin, TX (US);

Inventors:

Charles J. Alpert, Cedar Park, TX (US);

David J. Hathaway, Underhill, VT (US);

William R. Migatz, Wappingers Falls, NY (US);

Gi-Joon Nam, Austin, TX (US);

Haoxing Ren, Austin, TX (US);

Paul G. Villarrubia, Austin, TX (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim clock structure. The latches are weighted based on wire distance from a source of the star object, and then re-placed using the weighting. The weighted placement and repartitioning may be iteratively repeated until a target number of bins is reached. The boundary of the latches in the final global placement is used to define a movebound for further detailed placement.


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