The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 2009
Filed:
Apr. 25, 2006
Kyunghoon Min, Palo Alto, CA (US);
Mark Chang, Los Altos, CA (US);
Ning Cheng, San Jose, CA (US);
Brian Osborn, San Jose, CA (US);
Kevin Song, Santa Clara, CA (US);
Fei Wang, San Jose, CA (US);
Angela Hui, Fremont, CA (US);
Hiroyuki Kinoshita, San Jose, CA (US);
Kuo-tung Chang, Saratoga, CA (US);
Kyunghoon Min, Palo Alto, CA (US);
Mark Chang, Los Altos, CA (US);
Ning Cheng, San Jose, CA (US);
Brian Osborn, San Jose, CA (US);
Kevin Song, Santa Clara, CA (US);
Fei Wang, San Jose, CA (US);
Angela Hui, Fremont, CA (US);
Hiroyuki Kinoshita, San Jose, CA (US);
Kuo-Tung Chang, Saratoga, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Abstract
A method for manufacturing a semiconductor device including selective conductive contacts includes the step of depositing a resist over first and second memory device components, each of the first and second components comprising junctions formed in the substrate and a gate formed on the substrate between the junctions. The resist is then removed from the second components to thereby form a resist opening above each of the second component control gates and junctions. The resist is then etched to thereby expose each of the first component control gates but not the substrate surrounding the first component control gates. Conductive contacts are then formed on the exposed first component control gates, and the second component control gates and junctions.