The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 2009
Filed:
Apr. 27, 2007
Eric A. Foreman, Fairfax, VT (US);
Gary D. Grise, Colchester, VT (US);
Peter A. Habitz, Hinesburg, VT (US);
Vikram Iyengar, South Burlington, VT (US);
David E. Lackey, Jericho, VT (US);
Chandramouli Visweswariah, Croton-on-Hudson, NY (US);
Jinjun Xiong, White Plains, NY (US);
Vladimir Zolotov, Putnam Valley, NY (US);
Eric A. Foreman, Fairfax, VT (US);
Gary D. Grise, Colchester, VT (US);
Peter A. Habitz, Hinesburg, VT (US);
Vikram Iyengar, South Burlington, VT (US);
David E. Lackey, Jericho, VT (US);
Chandramouli Visweswariah, Croton-on-Hudson, NY (US);
Jinjun Xiong, White Plains, NY (US);
Vladimir Zolotov, Putnam Valley, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage.