The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 2009
Filed:
Feb. 16, 2006
Daniel Douriet, Round Rock, TX (US);
Anand Haridass, Austin, TX (US);
Andreas Huber, Holzgerlingen, DE;
Colm B. O'reilly, Austin, TX (US);
Roger D. Weekly, Austin, TX (US);
Daniel Douriet, Round Rock, TX (US);
Anand Haridass, Austin, TX (US);
Andreas Huber, Holzgerlingen, DE;
Colm B. O'Reilly, Austin, TX (US);
Roger D. Weekly, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A low inductance via arrangement for multilayer ceramic (MLC) substrates is provided. With the MLC substrate and via arrangement of the illustrative embodiments, the via-field inductance for a given contact pad array is reduced. This reduction is achieved by the introduction of T-jogs and additional vias. These T-jogs and additional vias form additional current paths that cause additional parallel inductances that reduce the via-field inductance. In one illustrative embodiment, the additional T-jogs and vias are added to a center portion of a contact pad array. The T-jogs are comprised of two jogs in a wiring layer of the MLC, each jog being toward a via associated with an adjacent contact pad in the contact pad array. These additional T-jogs and vias form additional current loops parallel to the existing ones which thus, reduce the total inductance of the via-field.