Robust deep trench isolation

Abstract

Higher voltage device isolation structures (') are provided for semiconductor integrated circuits having strongly doped buried layers (″). One or more dielectric lined deep isolation trenches (′″) separates adjacent device regions (). Electrical breakdown (BVdss) between the device regions () and the oppositely doped substrate (″) is found to occur preferentially where the buried layer (″) intersects the dielectric sidewalls (″) of the trench (′″). The breakdown voltage (BVdss) is increased by providing a more lightly doped region () of the same conductivity type as the buried layer (″), underlying the buried layer (″) at the trench sidewalls (″). The more lightly doped region's () dopant concentration is desirably 1E4 to 2E2 times less than the buried layer (″) and it extends substantially entirely beneath the buried layer (″) or to a distance () extending about 0.5 to 2.0 micro-meters from the trench sidewall (″). In a preferred embodiment, the trench (′) is split into two portions (′) with the semiconductor therein () ohmically coupled to the substrate ().