The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2009
Filed:
Dec. 28, 2004
Mark Allen Boike, Plano, TX (US);
Seshagiri Prasad Kalluri, Richardson, TX (US);
Vijayanand J. Angarai, Richardson, TX (US);
David Mark Brantley, Flower Mound, TX (US);
Scott Avery Beeker, Coppell, TX (US);
Mark Allen Boike, Plano, TX (US);
Seshagiri Prasad Kalluri, Richardson, TX (US);
Vijayanand J. Angarai, Richardson, TX (US);
David Mark Brantley, Flower Mound, TX (US);
Scott Avery Beeker, Coppell, TX (US);
LSI Corporation, Milpitas, CA (US);
Abstract
An apparatus and method are disclosed for testing a hard macro that is embedded in a system on a chip (SOC) that is included in an integrated circuit chip. The SOC includes the hard macro. A logic design and operation of the hard macro are unknown. A test wrapper is embedded in the SOC. The test wrapper includes a scan chain. The test wrapper surrounds inputs and outputs of the hard macro. The test wrapper receives a known test data pattern in the scan chain that is included in the test wrapper. The hard macro receives from the test wrapper a set of non-test standard SOC inputs when the SOC is not in a test mode and receives the known test data pattern when the SOC is in the test mode. The hard macro generates a set of outputs in response to the inputs. The hard macro is tested utilizing the known test data pattern.