The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2009
Filed:
Dec. 19, 2005
Applicants:
Bratin Saha, San Jose, CA (US);
Hariharan L. Thantry, Santa Clara, CA (US);
Ali-reza Adl-tabatabai, Santa Clara, CA (US);
Inventors:
Bratin Saha, San Jose, CA (US);
Hariharan L. Thantry, Santa Clara, CA (US);
Ali-Reza Adl-Tabatabai, Santa Clara, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
According to one embodiment of the invention, a method comprises verifying that a cache block is not exclusively owned, and if not, transmitting a message identifying both the cache block and a caching agent requesting ownership of the cache block to a broadcast interconnect.
Saha, Bratin. (2009). System and method for reducing store latency (U.S. Patent No. 7606981). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7606981
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile