The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2009
Filed:
Aug. 03, 2006
Ming H. Ding, San Jose, CA (US);
Sajitha Wijesuriya, Macungie, PA (US);
Jun Zhao, Allentown, PA (US);
OM P. Agrawal, Los Altos, CA (US);
Barry Britton, Orefield, PA (US);
Xiaojie He, Austin, TX (US);
Ming H. Ding, San Jose, CA (US);
Sajitha Wijesuriya, Macungie, PA (US);
Jun Zhao, Allentown, PA (US);
Om P. Agrawal, Los Altos, CA (US);
Barry Britton, Orefield, PA (US);
Xiaojie He, Austin, TX (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
Systems and methods provide programmable logic block architectures and routing architectures for the programmable logic blocks. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks. A first routing circuit provides global signal routing within the programmable logic device for the corresponding programmable logic block. A first input routing circuit receives signals from the first routing circuit and routes the signals to the logic block slices within the corresponding programmable logic block.