The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2009
Filed:
Jan. 25, 2007
Tse E. Wong, Los Alamitos, CA (US);
Samuel D. Tonomura, Rancho Palos Verdes, CA (US);
Stephen E. Sox, La Canada, CA (US);
Timothy E. Dearden, Torrance, CA (US);
Clifton Quan, Arcadia, CA (US);
Polwin C. Chan, Monterey Park, CA (US);
Mark S. Hauhe, Hermosa Beach, CA (US);
Tse E. Wong, Los Alamitos, CA (US);
Samuel D. Tonomura, Rancho Palos Verdes, CA (US);
Stephen E. Sox, La Canada, CA (US);
Timothy E. Dearden, Torrance, CA (US);
Clifton Quan, Arcadia, CA (US);
Polwin C. Chan, Monterey Park, CA (US);
Mark S. Hauhe, Hermosa Beach, CA (US);
Raytheon Company, Waltham, MA (US);
Abstract
A stacked integrated circuit assembly includes a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC is disposed between the substrate and the SFIC. The stacked integrated circuit assembly includes least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.