The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2009

Filed:

Dec. 19, 2006
Applicants:

Gerhard Schrom, Hillsboro, OR (US);

Dinesh Somasekhar, Portland, OR (US);

Fabrice Paillet, Hillsboro, OR (US);

Peter Hazucha, Beaverton, OR (US);

Sung Tae Moon, Hillsboro, OR (US);

Tanay Karnik, Portland, OR (US);

Inventors:

Gerhard Schrom, Hillsboro, OR (US);

Dinesh Somasekhar, Portland, OR (US);

Fabrice Paillet, Hillsboro, OR (US);

Peter Hazucha, Beaverton, OR (US);

Sung Tae Moon, Hillsboro, OR (US);

Tanay Karnik, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 27/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A signal generating circuit is provided. The signal generating circuit may include a plurality of delay circuits coupled to provide a plurality of control signals, a weighted-sum circuit to receive the plurality of control signals and to provide an output analog signal, and a comparator circuit to compare the output analog signal with a voltage and to provide a pulse width modulated (PWM) signal based on the comparison.


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