The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2009
Filed:
Jan. 17, 2007
Yang-soo Son, Yongin-si, KR;
Young-seop Rah, Yongin-si, KR;
Won-seok Cho, Suwon-si, KR;
Soon-moon Jung, Seongnam-si, KR;
Jae-hoon Jang, Seongnam-si, KR;
Young-chul Jang, Yongin-si, KR;
Yang-Soo Son, Yongin-si, KR;
Young-Seop Rah, Yongin-si, KR;
Won-Seok Cho, Suwon-si, KR;
Soon-Moon Jung, Seongnam-si, KR;
Jae-Hoon Jang, Seongnam-si, KR;
Young-Chul Jang, Yongin-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
A NAND flash memory device includes a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer, a first drain region and a first source region located in the lower semiconductor layer, and a second drain region and a second source region located in the upper semiconductor layer. A first gate structure is located on the lower semiconductor layer, and a second gate structure is located on the upper semiconductor layer. A bit line is located over the upper semiconductor layer, and at least one bit line plug is connected between the bit line and the first drain region, where the at least one bit line plug extends through a drain throughhole located in the upper semiconductor layer.