The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2009
Filed:
Dec. 07, 2007
Applicants:
Robert Herrick, Lehi, UT (US);
Dean Probst, West Jordan, UT (US);
Fred Session, Sandy, UT (US);
Inventors:
Assignee:
Fairchild Semiconductor Corporation, South Portland, ME (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method of forming shielded gate trench FET includes the following steps. A trench is formed in a silicon region of a first conductivity type. A shield electrode is formed in a bottom portion of the trench. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer of conformal dielectric is formed along an upper surface of the shield electrode. A gate dielectric lining at least upper trench sidewalls is formed. A gate electrode is formed in the trench such that the gate electrode is insulated from the shield electrode by the IPD.