The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2009
Filed:
Jun. 30, 2008
OM P. Agrawal, Los Altos, CA (US);
Xiaojie He, Austin, TX (US);
Sajitha Wijesuriya, Macungie, PA (US);
Barry Britton, Orefield, PA (US);
Ming H. Ding, San Jose, CA (US);
Jun Zhao, Allentown, PA (US);
Om P. Agrawal, Los Altos, CA (US);
Xiaojie He, Austin, TX (US);
Sajitha Wijesuriya, Macungie, PA (US);
Barry Britton, Orefield, PA (US);
Ming H. Ding, San Jose, CA (US);
Jun Zhao, Allentown, PA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
In one embodiment of the invention, a programmable logic device comprises configuration memory adapted to store configuration data and a plurality of programmable logic blocks. At least one programmable logic block includes a plurality of dual-slice logic blocks, each dual-slice logic block including first and second slices, each slice including at least two lookup tables (LUTs) and a register. The programmable logic block further includes control logic adapted for selecting control signals separately at a programmable block level, a dual-slice block level, and a register level, the control logic responsive to configuration data stored within the configuration memory.