The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2009
Filed:
Dec. 10, 2007
Gong-heum Han, Gyeonggi-do, KR;
Hyou-youn Nam, Gyeonggi-do, KR;
Bo-tak Lim, Gyeonggi-do, KR;
Han-byung Park, Gyeonggi-do, KR;
Soon-moon Jung, Gyeonggi-do, KR;
Hoon Lim, Seoul, KR;
Gong-Heum Han, Gyeonggi-do, KR;
Hyou-Youn Nam, Gyeonggi-do, KR;
Bo-Tak Lim, Gyeonggi-do, KR;
Han-Byung Park, Gyeonggi-do, KR;
Soon-Moon Jung, Gyeonggi-do, KR;
Hoon Lim, Seoul, KR;
Abstract
A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.