The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2009
Filed:
Oct. 19, 2007
Yuichi Morita, Kanagawa, JP;
Takashi Noma, Gunma, JP;
Hiroyuki Shinogi, Gunma, JP;
Shinzo Ishibe, Gunma, JP;
Katsuhiko Kitagawa, Gunma, JP;
Noboru Okubo, Saitama, JP;
Kazuo Okada, Gunma, JP;
Hiroshi Yamada, Gunma, JP;
Yuichi Morita, Kanagawa, JP;
Takashi Noma, Gunma, JP;
Hiroyuki Shinogi, Gunma, JP;
Shinzo Ishibe, Gunma, JP;
Katsuhiko Kitagawa, Gunma, JP;
Noboru Okubo, Saitama, JP;
Kazuo Okada, Gunma, JP;
Hiroshi Yamada, Gunma, JP;
Sanyo Electric Co., Ltd., Osaka, JP;
Sanyo Semiconductor Co., Ltd., Gunma, JP;
Abstract
The invention is directed to providing a package type semiconductor device with high reliability and smaller size and a method of manufacturing the same. A semiconductor substrate formed with a device element and a pad electrode on its front surface is prepared. The semiconductor substrate is then selectively etched from its back surface to form an opening. A second insulation film is then formed covering the side and back surfaces of the semiconductor substrate. First and second insulation films on the bottom of the opening are then selectively removed to expose a portion of the pad electrode. A wiring layer is then formed along the side surface of the semiconductor substrate, being electrically connected with the exposed pad electrode. An electrode connect layer is then formed covering the wiring layer. A protection layer is then formed covering the back surface of the semiconductor substrate and having an opening in a region for formation of a sidewall electrode. Then, the sidewall electrode is formed in a region exposed by the opening of the protection layer.