The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2009
Filed:
Jul. 12, 2006
Sung Mun Jung, Singapore, SG;
Yoke Leng Louis Lim, Singapore, SG;
Sripad Nagarad, Singapore, SG;
Dong Kyun Sohn, Singapore, SG;
Dong Hua Liu, Singapore, SG;
Xiao Yu Chen, Singapore, SG;
Rachel Low, Singapore, SG;
Sung Mun Jung, Singapore, SG;
Yoke Leng Louis Lim, Singapore, SG;
Sripad Nagarad, Singapore, SG;
Dong Kyun Sohn, Singapore, SG;
Dong Hua Liu, Singapore, SG;
Xiao Yu Chen, Singapore, SG;
Rachel Low, Singapore, SG;
Chartered Semiconductor Manufacturing, Ltd., Singapore, SG;
Abstract
In an non-limiting example, we provide a substrate having a cell region, and non-cell regions. We form a tunneling dielectric layer, a charge storing layer, a top insulating layer (e.g., ONO), over the substrate. Then we form a conductive pad layer over the top insulating layer. We form isolation trenches in the pad layer, the charge storing layer and the tunneling dielectric layer and into the substrate. We form isolation regions in the isolation trenches. We remove the pad layer, charge storing layer and the tunneling dielectric layer in the non-cell regions. We form a gate layer over the pad layer and the substrate surface. We complete to form the memory (e.g., SONOS) device in the cell region and other devices in the non-cell regions of the substrate.