The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2009

Filed:

Jan. 26, 2006
Applicants:

Moon-chul Lee, Yongin-si, KR;

Woon-bae Kim, Suwon-si, KR;

Kae-dong Back, Yongin-si, KR;

Qian Wang, Yongin-si, KR;

Jun-sik Hwang, Yongin-si, KR;

Kyu-dong Jung, Suwon-si, KR;

Inventors:

Moon-chul Lee, Yongin-si, KR;

Woon-bae Kim, Suwon-si, KR;

Kae-dong Back, Yongin-si, KR;

Qian Wang, Yongin-si, KR;

Jun-sik Hwang, Yongin-si, KR;

Kyu-dong Jung, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/12 (2006.01); H01L 23/043 (2006.01);
U.S. Cl.
CPC ...
Abstract

A wafer level packaging cap and method thereof for a wafer level packaging are provided. The wafer level packaging cap covering a device wafer with a device thereon, includes a cap wafer having on a bottom surface a cavity providing a space for receiving the device, and integrally combined with the device wafer, a plurality of metal lines formed on the bottom surface of the cap wafer to correspond to a plurality of device pads formed on the device wafer to be electrically connected to the device, a plurality of buffer portions connected to the plurality of metal lines and comprising a buffer wafer with a plurality of grooves and a metal filled in the plurality of grooves, a plurality of connection rods electrically connected to the plurality of buffer portions and penetrating the cap wafer from a top portion of the buffer portion, and a plurality of cap pads formed on a top surface of the cap wafer and electrically connected to a plurality of connection rods.


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