The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2009

Filed:

Dec. 01, 2006
Applicants:

Kenji Yoshida, Tokyo, JP;

Takashi Mitsuhashi, Fujisawa, JP;

Shohei Matsushita, Yokohama, JP;

Akira Fujimura, Saratoga, CA (US);

Inventors:

Kenji Yoshida, Tokyo, JP;

Takashi Mitsuhashi, Fujisawa, JP;

Shohei Matsushita, Yokohama, JP;

Akira Fujimura, Saratoga, CA (US);

Assignee:

D2S, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G21K 5/04 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for particle beam lithography, such as electron beam (EB) lithography, includes predefining a stencil design having a plurality of cell patterns with information from a cell library, fabricating the stencil design, synthesizing a functional description into a logic circuit design after predefining the stencil design so that one or more characteristics of the stencil design are considered during synthesizing of the functional description into the logic circuit design, optimizing the logic circuit design, generating a layout design from the optimized logic circuit design, and forming the logic circuit on a substrate according to the stencil design and the layout design.


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