The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2009

Filed:

Aug. 21, 2007
Applicants:

Kenichi Koyanagi, Tokyo, JP;

Takashi Arao, Tokyo, JP;

Inventors:

Kenichi Koyanagi, Tokyo, JP;

Takashi Arao, Tokyo, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/31 (2006.01); H01L 21/469 (2006.01); H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

An objective of this invention is to solve the problem that in ALD film deposition using a vertical batch processing machine advantageous for improving a throughput, reliability in a dielectric body formed on the bottom of a hole such as a capacitor formed on a semiconductor substrate is reduced as the hole is finer and deeper. A dielectric body is formed by an ALD film deposition process comprising a gas flow sequence where a purging step after supplying a source and a reactant gases is a two-stage purging of vacuum purging and gas purging and the step of supplying a reactant gas is further divided. The process allows a highly reliable dielectric body to be formed in the bottom of a deep hole, contributing to improvement in reliability of a capacitor and a semiconductor device.


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