The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2009

Filed:

Sep. 07, 2006
Applicants:

Herbert L. Ho, New Windsor, NY (US);

Kangguo Cheng, Beacon, NY (US);

Yoichi Otani, Bargen BE, CH;

Kevin R. Winstel, Poughkeepsie, NY (US);

Inventors:

Herbert L. Ho, New Windsor, NY (US);

Kangguo Cheng, Beacon, NY (US);

Yoichi Otani, Bargen BE, CH;

Kevin R. Winstel, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of forming a deep trench capacitor through an SOI substrate, and a capacitor are disclosed. In one embodiment, a method includes forming a trench opening into the SOI substrate to the silicon substrate; depositing a sidewall spacer in the trench opening; etching to form the deep trench into the silicon substrate; forming a first electrode by implanting a dopant into the silicon substrate, whereby the sidewall spacer protects the BOX layer and the silicon layer; removing the sidewall spacer; depositing a node dielectric within the deep trench; and forming a second electrode by depositing a conductor in the deep trench. Implanting creates a substantially uniform depth doped region except at a portion adjacent to a lowermost portion of the deep trench, which may be substantially bulbous. The BOX layer is protected from undercutting by the sidewall spacer, and the implantation removes the need for out-diffusing dopant from silica glass.


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