The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 2009
Filed:
Apr. 30, 2007
Mariam G. Sadaka, Austin, TX (US);
Debby Eades, Manor, TX (US);
Joe Mogab, Austin, TX (US);
Bich-yen Nguyen, Austin, TX (US);
Melissa O. Zavala, Pflugerville, TX (US);
Gregory S. Spencer, Pflugerville, TX (US);
Mariam G. Sadaka, Austin, TX (US);
Debby Eades, Manor, TX (US);
Joe Mogab, Austin, TX (US);
Bich-Yen Nguyen, Austin, TX (US);
Melissa O. Zavala, Pflugerville, TX (US);
Gregory S. Spencer, Pflugerville, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor process and apparatus provide a high performance CMOS devices () with hybrid or dual substrates by etching a deposited oxide layer () using inverse slope isolation techniques to form tapered isolation regions () and expose underlying semiconductor layers () in a bulk wafer structure prior to epitaxially growing the first and second substrates () having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes () over a first substrate () that is formed by epitaxially growing (100) silicon and forming second gate electrodes () over a second substrate () that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.