The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2009
Filed:
Sep. 17, 2004
Richard M. Barth, Palo Alto, CA (US);
Ely K. Tsern, Los Altos, CA (US);
Craig E. Hampel, San Jose, CA (US);
Frederick A. Ware, Los Altos Hills, CA (US);
Todd W. Bystrom, Sunnyvale, CA (US);
Bradley A. May, San Jose, CA (US);
Paul G. Davis, San Jose, CA (US);
Richard M. Barth, Palo Alto, CA (US);
Ely K. Tsern, Los Altos, CA (US);
Craig E. Hampel, San Jose, CA (US);
Frederick A. Ware, Los Altos Hills, CA (US);
Todd W. Bystrom, Sunnyvale, CA (US);
Bradley A. May, San Jose, CA (US);
Paul G. Davis, San Jose, CA (US);
Rambus Inc., Los Altos, CA (US);
Abstract
A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode is provided in an embodiment. The command specifies an access to the array of memory cells. A delay lock loop circuit synchronizes data transfers using an external clock signal. The delay lock loop circuit reacquires synchronization with the external clock signal during the period of time.