The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2009
Filed:
Dec. 22, 2006
Karen H. R. Kirmse, Richardson, TX (US);
Yuanning Chen, Plano, TX (US);
Jarvis B. Jacobs, Murphy, TX (US);
Deborah J. Riley, Murphy, TX (US);
Karen H. R. Kirmse, Richardson, TX (US);
Yuanning Chen, Plano, TX (US);
Jarvis B. Jacobs, Murphy, TX (US);
Deborah J. Riley, Murphy, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The present invention provides a method for manufacturing a semiconductor device, which includes forming a gate structure over a substrate, and forming a stack of layers on the substrate and at least partially along a sidewall of the gate structure. In this embodiment, the stack of layers includes an initial layer located over the substrate, a buffer layer located over the initial layer and an offset layer located over the buffer layer. This embodiment of the method further includes removing horizontal segments of the offset layer and the buffer layer using a dry etch and a wet clean, wherein removing includes choosing at least one of an initial thickness of the buffer layer, a period of time for the dry etch or a period of time for the wet clean such that horizontal segments of the initial layer are exposed and substantially unaffected after the dry etch and wet clean.