The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2009

Filed:

Apr. 24, 2007
Applicants:

Christoph Schwan, Gebhardshain, DE;

Manfred Horstmann, Duerrrhoehrsdorf-Dittersbach, DE;

Kai Frohberg, Niederau, DE;

Rolf Stephan, Dresden, DE;

Inventors:

Christoph Schwan, Gebhardshain, DE;

Manfred Horstmann, Duerrrhoehrsdorf-Dittersbach, DE;

Kai Frohberg, Niederau, DE;

Rolf Stephan, Dresden, DE;

Assignee:

Advanced Micro Devices, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/31 (2006.01); H01L 21/469 (2006.01);
U.S. Cl.
CPC ...
Abstract

By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or dummy gates, wherein well-established gate patterning processes may be used or wherein nano-imprint techniques may be employed. Hence, in some illustrative embodiments, a significant increase of strain may be obtained on the basis of well-established process techniques.


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