The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2009

Filed:

Feb. 22, 2006
Applicants:

Anadi Srivastava, Austin, TX (US);

Mark D. Hall, Austin, TX (US);

Raghaw S. Rai, Austin, TX (US);

Jesse Yanez, New Braunfels, TX (US);

Inventors:

Anadi Srivastava, Austin, TX (US);

Mark D. Hall, Austin, TX (US);

Raghaw S. Rai, Austin, TX (US);

Jesse Yanez, New Braunfels, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method is provided for making a silicided gate (). In accordance with the method, a semiconductor structure () is provided which comprises a semiconductor substrate (), a gate () disposed on the semiconductor substrate, and a spacer () adjacent to the gate. The structure is subjected to a first etch which exposes a first lateral portion of the gate. An implant () is then created in a region adjacent to the spacer. The structure is then subjected to a second etch which exposes a second lateral portion of the gate electrode, and a layer of silicide () is formed which extends over the first and second lateral portions of the gate.


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