The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2009

Filed:

Nov. 13, 2006
Applicants:

Kangguo Cheng, Beacon, NY (US);

Richard O. Henry, Poughkeepsie, NY (US);

Kenneth T. Settlemyer, Jr., Bradeonton, FL (US);

Inventors:

Kangguo Cheng, Beacon, NY (US);

Richard O. Henry, Poughkeepsie, NY (US);

Kenneth T. Settlemyer, Jr., Bradeonton, FL (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01); H01L 21/336 (2006.01); H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the upper trench portion beyond the exposed upper surface of the semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer.


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