Semiconductor storage device

Abstract

A testing device for a semiconductor storage device which suppresses the increase in the circuit size, provides for facilitated accommodation to a test with frequent changes in the test pattern, and which improves testability of the semiconductor storage device. A plural number of holding circuits () are provided holding write data for memory cells of a memory cell array (-). The write data from the holding circuits () are written in the memory cells of the selected address. A plural number of comparators (CCMPN) are supplied with data read out from the memory cells and with data held by the holding circuits as expectation data to compare the readout data and the expectation data. The non-inverted value or the inverted value of the write data held by the holding circuits () is output as the write data to the memory cells and as expectation data to the comparators (CCMPN) depending on the value of the inversion control signal (DIM). A decision circuit () is provided which outputs an error flag based on a coincidence detection signal (MATCH) coupled to the plural comparators.