Cycling improvement using higher erase bias

Abstract

Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cells for a predetermined number of gate pulses or until all the memory cells are erased. In another embodiment, an erase bias circuit is provided for erasing a sector of flash memory cells, the circuit comprising row and column decoders that selects wordline rows and columns of cells, respectively, a supply bias arrangement that provides source and drain supply voltages for the sector, and a patterned pulse bias arrangement configured to provide a pulsed gate voltage pattern to gates of the cells selected by the row decoder and a drain voltage pattern to the drains of the cells selected by the column decoder.