The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2009
Filed:
Jan. 24, 2007
Rajesh Khamankar, Coppell, TX (US);
Douglas T. Grider, McKinney, TX (US);
Hiroaki Niimi, Austin, TX (US);
April Gurba, Allen, TX (US);
Toan Tran, Rowlett, TX (US);
James J. Chambers, Dallas, TX (US);
Rajesh Khamankar, Coppell, TX (US);
Douglas T. Grider, McKinney, TX (US);
Hiroaki Niimi, Austin, TX (US);
April Gurba, Allen, TX (US);
Toan Tran, Rowlett, TX (US);
James J. Chambers, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer () is formed on a semiconductor substrate (). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer () is removed in regions of the substrate and a second dielectric layer () is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors () are then fabricated using the dielectric layers ().