The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2009
Filed:
May. 05, 2006
Anda C. Mocuta, LaGrangeville, NY (US);
Dureseti Chidambarrao, Weston, CT (US);
Ricardo A. Donaton, Cortlandt Manor, NY (US);
David M. Onsongo, Newburgh, NY (US);
Kern Rim, Yorktown Heights, NY (US);
Anda C. Mocuta, LaGrangeville, NY (US);
Dureseti Chidambarrao, Weston, CT (US);
Ricardo A. Donaton, Cortlandt Manor, NY (US);
David M. Onsongo, Newburgh, NY (US);
Kern Rim, Yorktown Heights, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A semiconductor structure and method of manufacturing a semiconductor device, and more particularly, an NFET device. The devices includes a stress receiving layer provided over a stress inducing layer with a material at an interface there between which reduces the occurrence and propagation of misfit dislocations in the structure. The stress receiving layer is silicon (Si), the stress inducing layer is silicon-germanium (SiGe) and the material is carbon which is provided by doping the layers during formation of the device. The carbon can be doped throughout the whole of the SiGe layer also.