The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2009

Filed:

Dec. 28, 2006
Applicants:

Muhammad M. Khellah, Tigard, OR (US);

Dinesh Somasekhar, Portland, OR (US);

Yibin YE, Portland, OR (US);

Nam Sung Kim, Portland, OR (US);

Vivek DE, Beaverton, OR (US);

Inventors:

Muhammad M. Khellah, Tigard, OR (US);

Dinesh Somasekhar, Portland, OR (US);

Yibin Ye, Portland, OR (US);

Nam Sung Kim, Portland, OR (US);

Vivek De, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.


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