The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2009

Filed:

Jun. 08, 2000
Applicants:

Vernon M. Williams, Meridian, ID (US);

Ford B. Grigg, Meridian, ID (US);

Bret K. Street, Meridian, ID (US);

Inventors:

Vernon M. Williams, Meridian, ID (US);

Ford B. Grigg, Meridian, ID (US);

Bret K. Street, Meridian, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A conductive structure configured to connect a contact pad of a semiconductor device with a corresponding contact pad of a substrate. The conductive structure includes two interconnectable members, one securable to each of the corresponding contact pads. Each member includes a dielectric jacket having an aperture that laterally confines conductive material of a conductive center thereof over the contact pad to which the member is secured. The conductive center of a female member of the conductive structure only partially fills the aperture of the jacket thereof so as to form a receptacle for an end of the male member of the conductive structure. One or both of the male and female members may also be configured to limit the insertion of the male member into the receptacle of the female member. The members of the conductive structure may be preformed structures which are attached to a surface of a semiconductor device or other substrate. Alternatively, the members can be fabricated on the surface of the semiconductor device or other substrate. A stereolithographic method of fabricating at least the jackets of the members is disclosed. The stereolithographic method may include use of a machine vision system including at least one camera operably associated with a computer controlling a stereolithographic application of material so that the system may recognize the position and orientation of a semiconductor device or other substrate on which a member of the conductive structure is to be fabricated. Methods of connecting a semiconductor device with another substrate are also disclosed, as are assemblies including the conductive structures.


Find Patent Forward Citations

Loading…