The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2009
Filed:
May. 26, 2005
Ankur Aggarwal, Smyrna, GA (US);
Isaac Robin Abothu, Atlanta, GA (US);
Pulugurtha Markondeya Raj, Atlanta, GA (US);
Rao R. Tummala, Stone Mountain, GA (US);
Ankur Aggarwal, Smyrna, GA (US);
Isaac Robin Abothu, Atlanta, GA (US);
Pulugurtha Markondeya Raj, Atlanta, GA (US);
Rao R. Tummala, Stone Mountain, GA (US);
Georgia Tech Research Corporation, Atlanta, GA (US);
Abstract
Nano-structured interconnect formation and a reworkable bonding process using solder films. Large area fabrication of nano-structured interconnects is demonstrated at a very fine pitch. This technology can be used for pushing the limits of current flip chip bonding in terms of pitch, number of I/Os, superior combination of electrical and mechanical properties as well as reworkability. Sol-gel and electroless processes were developed to demonstrate film bonding interfaces between metallic pads and nano interconnects. Solution-derived nano-solder technology is an attractive low-cost method for several applications such as MEMS hermetic packaging, compliant interconnect bonding and bump-less nano-interconnects.