The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2009
Filed:
Jun. 30, 2006
Qing a Zhou, Chandler, AZ (US);
Daoqiang LU, Chandler, AZ (US);
Wei Shi, Gilbert, AZ (US);
Jiangqi He, Gilbert, AZ (US);
Qing A Zhou, Chandler, AZ (US);
Daoqiang Lu, Chandler, AZ (US);
Wei Shi, Gilbert, AZ (US);
Jiangqi He, Gilbert, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An integrated circuit ('IC') package having two or more dice stacked on a substrate and electrically coupled using two or more different connection technologies may improve high-speed input/output ('I/O') bandwidth. In an embodiment, one die is a processor and at least one other die is a dynamic random access memory (“DRAM”). One or more of the dice may be thinned and placed between the substrate and a portion of one or more of the other dice, which may be horizontally offset. One or more of the dice may be embedded in the substrate. The dice may be coupled to each other and to the substrate using a combination of controlled-collapse chip connection (“C4”) and wirebonding connection technologies. Methods of fabrication, and application of the package to an electronic assembly and to an electronic system, are also described.