The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2009
Filed:
Aug. 16, 2006
Yasuo Osone, Kasumigaura, JP;
Chiko Yorita, Fujisawa, JP;
Kenya Kawano, Hitachinaka, JP;
Yu Hasegawa, Saku, JP;
Yuji Shirai, Hamura, JP;
Seiichi Tomoi, Saku, JP;
Tsuneo Endou, Komoro, JP;
Satoru Konishi, Saku, JP;
Hirokazu Nakajima, Saku, JP;
Yasuo Osone, Kasumigaura, JP;
Chiko Yorita, Fujisawa, JP;
Kenya Kawano, Hitachinaka, JP;
Yu Hasegawa, Saku, JP;
Yuji Shirai, Hamura, JP;
Seiichi Tomoi, Saku, JP;
Tsuneo Endou, Komoro, JP;
Satoru Konishi, Saku, JP;
Hirokazu Nakajima, Saku, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A semiconductor device capable of reducing the thermal resistance in a flip chip packaging structure while achieving both the high radiation performance and manufacturing readiness without increasing the manufacturing cost is provided. In a semiconductor device having a semiconductor circuit for power amplification and a control circuit of the semiconductor circuit laminated on a multilayer circuit board, the semiconductor circuit for power amplification and the control circuit are aligned in parallel on the same semiconductor element, and the semiconductor element is flip-chip connected on the multilayer circuit board. Further, a second semiconductor element mounted in addition to the first semiconductor element and all components and submodules are flip-chip connected. Also, a plurality of bumps are united in order to improve the radiation performance and thermal vias of the multilayer circuit board are formed in second and lower layers of the wiring layers in the multilayer circuit board.