The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2009
Filed:
Sep. 18, 2006
Wan-jae Park, Seoul, KR;
Hyung-yoon Choi, Gyeonggi-do, KR;
Yi-hsiung Lin, Taipei, TW;
Tong Qing Chen, Singapore, CN;
Wan-jae Park, Seoul, KR;
Hyung-yoon Choi, Gyeonggi-do, KR;
Yi-hsiung Lin, Taipei, TW;
Tong Qing Chen, Singapore, CN;
Samsung Electronics Co., Ltd., , KR;
Chartered Semiconductor Manufacturing Ltd., Singapore, SG;
International Business Machines Corporation, Armonk, NY (US);
Abstract
Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower interconnection, forming an etch stopper layer and an interlayer dielectric layer on the semiconductor substrate, forming a via hole in the interlayer dielectric layer so that the etch stopper layer is exposed through the via hole, performing carbon doping on the etch stopper layer, performing trench etching to form a trench in the interlayer dielectric layer so that the trench overlaps part of the via hole, removing the carbon-doped etch stopper layer, and filling the via hole and the trench with a conductive material to form an upper interconnection.