The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2009

Filed:

May. 22, 2008
Applicants:

Chrong-jung Lin, Taipei Hsien, TW;

Hsin-ming Chen, Tainan Hsien, TW;

Shih-jye Shen, Hsin-Chu, TW;

Ya-chin King, Tao-Yuan Hsien, TW;

Ching-hsiang Hsu, Hsin-Chu, TW;

Inventors:

Chrong-Jung Lin, Taipei Hsien, TW;

Hsin-Ming Chen, Tainan Hsien, TW;

Shih-Jye Shen, Hsin-Chu, TW;

Ya-Chin King, Tao-Yuan Hsien, TW;

Ching-Hsiang Hsu, Hsin-Chu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls of the gate, a Psource doping region and a Pdrain doping region. The ONO layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.


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