The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2009
Filed:
Apr. 05, 2007
Applicants:
Harsh Chilwal, Bangalore, IN;
Srikanth Jadcherla, Saratoga, CA (US);
Sriram Kotni, Fremont, CA (US);
Prapanna Tiwari, Sunnyvale, CA (US);
Inventors:
Harsh Chilwal, Bangalore, IN;
Srikanth Jadcherla, Saratoga, CA (US);
Sriram Kotni, Fremont, CA (US);
Prapanna Tiwari, Sunnyvale, CA (US);
Assignee:
Synopsys, Inc., Mountain View, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract
Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.