The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2009

Filed:

Aug. 18, 2006
Applicants:

Stuart E. Wilson, Menlo Park, CA (US);

Ronald Green, San Jose, CA (US);

Richard Dewitt Crisp, Castro Valley, CA (US);

Giles Humpston, Aylesbury, GB;

Inventors:

Stuart E. Wilson, Menlo Park, CA (US);

Ronald Green, San Jose, CA (US);

Richard Dewitt Crisp, Castro Valley, CA (US);

Giles Humpston, Aylesbury, GB;

Assignee:

Tessera, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H05K 7/00 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A stacked microelectronic assembly includes a base substrate having conductive elements projecting from a bottom surface thereof and a first microelectronic subassembly underlying a bottom surface of the base substrate. The first microelectronic subassembly includes a first dielectric substrate, a first microelectronic element connected with the first dielectric substrate and first conductive posts projecting from the first dielectric substrate toward the bottom surface of the base substrate for electrically interconnecting the first microelectronic element and the base substrate. The assembly also has a second microelectronic subassembly overlying the base substrate. The second microelectronic subassembly includes a second dielectric substrate, a second microelectronic element connected with the second dielectric substrate and second conductive posts projecting toward the top surface of the base substrate for electrically interconnecting the second microelectronic element and the base substrate. The first microelectronic subassembly has a first height and the conductive elements projecting from the bottom surface of the base substrate have a second height that is greater than the first height of the first microelectronic subassembly.


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