The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2009

Filed:

Sep. 07, 2004
Applicants:

Cyril Cabral, Jr., Mahopac, NY (US);

Michael A. Cobb, Croton on Hudson, NY (US);

Asa Frye, LaGrangeville, NY (US);

Balasubramanian S. Pranatharthi Haran, Yorktown Heights, NY (US);

Randolph F. Knarr, Goldens Bridge, NY (US);

Mahadevaiyer Krishnan, Hopewll Junction, NY (US);

Christian Lavoie, Ossining, NY (US);

Andrew P. Mansson, Gilbert, AZ (US);

Renee T. MO, Briarcliff Manor, NY (US);

Jay W. Strane, Wappingers Falls, NY (US);

Horatio S. Wildman, Wappingers Falls, NY (US);

Inventors:

Cyril Cabral, Jr., Mahopac, NY (US);

Michael A. Cobb, Croton on Hudson, NY (US);

Asa Frye, LaGrangeville, NY (US);

Balasubramanian S. Pranatharthi Haran, Yorktown Heights, NY (US);

Randolph F. Knarr, Goldens Bridge, NY (US);

Mahadevaiyer Krishnan, Hopewll Junction, NY (US);

Christian Lavoie, Ossining, NY (US);

Andrew P. Mansson, Gilbert, AZ (US);

Renee T. Mo, Briarcliff Manor, NY (US);

Jay W. Strane, Wappingers Falls, NY (US);

Horatio S. Wildman, Wappingers Falls, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/477 (2006.01); H01L 21/441 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiOand SiNis not converted into a metal alloy silicide contact during the annealing step. A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.


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