The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2009
Filed:
Jun. 14, 2007
Toshiyuki Enda, Zushi, JP;
Hiroyoshi Tanimoto, Yokohama, JP;
Naoki Kusunoki, Fuchu, JP;
Nobutoshi Aoki, Yokohama, JP;
Fumitaka Arai, Yokohama, JP;
Riichiro Shirota, Fujisawa, JP;
Toshiyuki Enda, Zushi, JP;
Hiroyoshi Tanimoto, Yokohama, JP;
Naoki Kusunoki, Fuchu, JP;
Nobutoshi Aoki, Yokohama, JP;
Fumitaka Arai, Yokohama, JP;
Riichiro Shirota, Fujisawa, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A non-volatile semiconductor memory includes a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.