The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2009
Filed:
Nov. 22, 2005
John Burns, Colorado Springs, CO (US);
Matthew A. Fuller, Colorado Springs, CO (US);
Jeffery J. King, Colorado Springs, CO (US);
Martin L. Forbes, Divide, CO (US);
Mark V. Smith, Colorado Springs, CO (US);
John Burns, Colorado Springs, CO (US);
Matthew A. Fuller, Colorado Springs, CO (US);
Jeffery J. King, Colorado Springs, CO (US);
Martin L. Forbes, Divide, CO (US);
Mark V. Smith, Colorado Springs, CO (US);
Entegris, Inc., Chaska, MN (US);
Abstract
A wafer container providing improved wafer restraint during physical shock events. In embodiments of the invention, a secondary wafer restraint structure defining a plurality of notches is interposed between opposing wafer restraint members on the door of the container. The notches may be defined by one or more converging edges or surfaces meeting at a junction. The junctions are positioned so as to align with the wafer receiving portions of each opposing pair of wafer restraint member so that when the door is fully sealingly engaged with the enclosure of the container, the edge of the wafer is contacting the junction. In this position, any vertical movement of the wafer due to shock imparted to the container causes the wafer to contact the converging surfaces or edges, thereby limiting such movement. The positioning of the secondary wafer restraint structure between and proximate opposing fingers of the primary wafer restraint limits deflection of the wafer between support points and thereby further inhibits the wafer from 'jumping' out of the supports and cross-slotting.