The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2009
Filed:
Dec. 20, 2007
Zhigang Wang, Sunnyvale, CA (US);
Gregory Bakker, San Jose, CA (US);
Volker Hecht, Barshinghausen, DE;
Santosh Yachareni, San Jose, CA (US);
Fethi Dhaoui, Patterson, CA (US);
Vidyadhara Bellippady, San Jose, CA (US);
Zhigang Wang, Sunnyvale, CA (US);
Gregory Bakker, San Jose, CA (US);
Volker Hecht, Barshinghausen, DE;
Santosh Yachareni, San Jose, CA (US);
Fethi Dhaoui, Patterson, CA (US);
Vidyadhara Bellippady, San Jose, CA (US);
Actel Corporation, Mountain View, CA (US);
Abstract
A non-volatile memory array segment includes an odd-select transistor having a drain coupled to an odd-source line and an even-select transistor having a drain coupled to an even-source line. Two segment-select transistors have drains coupled to the sources of different ones of the odd and even source lines, sources coupled to ground, and gates coupled to a segment-select line. A plurality of odd non-volatile memory transistors each has a drain coupled to a common drain line, a source coupled to the odd-source line, a floating gate, and a control gate. A plurality of even non-volatile memory transistors, each has a drain coupled to the common drain line, a source coupled to the even-source line, a floating gate, and a control gate. The control gate of each even non-volatile memory transistor is coupled to the control gate of a different one of the odd non-volatile memory transistors.