The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2009

Filed:

Jan. 11, 2005
Applicants:

Jae-hoon Jang, Gyeonggi-do, KR;

Soon-moon Jung, Gyeonggi-do, KR;

Kun-ho Kwak, Gyeonggi-do, KR;

Byung-jun Hwang, Gyeonggi-do, KR;

Inventors:

Jae-Hoon Jang, Gyeonggi-do, KR;

Soon-Moon Jung, Gyeonggi-do, KR;

Kun-Ho Kwak, Gyeonggi-do, KR;

Byung-Jun Hwang, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
Abstract

A static random-access memory (SRAM) device may include a bulk MOS transistor on a semiconductor substrate having a source/drain region therein, an insulating layer on the bulk MOS transistor, and a thin-film transistor having a source/drain region therein on the insulating layer above the bulk MOS transistor. The device may further include a multi-layer plug between the bulk MOS transistor and the thin-film transistor. The multi-layer plug may include a semiconductor plug directly on the source/drain region of the bulk MOS transistor and extending through at least a portion of the insulating layer, and a metal plug directly on the source/drain region of the thin-film transistor and the semiconductor plug and extending through at least a portion of the insulating layer. Related methods are also discussed.


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