The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2009
Filed:
Apr. 12, 2007
Masayoshi Okamoto, Kai, JP;
Hideyuki Matsumoto, Higashimurayama, JP;
Shingo Yorisaki, Hachioji, JP;
Akio Hasebe, Kodaira, JP;
Yasuhiro Motoyama, Hachioji, JP;
Akira Shimase, Yokosuka, JP;
Masayoshi Okamoto, Kai, JP;
Hideyuki Matsumoto, Higashimurayama, JP;
Shingo Yorisaki, Hachioji, JP;
Akio Hasebe, Kodaira, JP;
Yasuhiro Motoyama, Hachioji, JP;
Akira Shimase, Yokosuka, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes, in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.