The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2009
Filed:
Dec. 21, 2006
Samed Halilov, Waltham, MA (US);
Xiangyang Huang, Waltham, MA (US);
Ilija Dukovski, Newtonville, MA (US);
Jean Augustin Chan Sow Fook Yiptong, Worchester, MA (US);
Robert J. Mears, Wellesley, MA (US);
Marek Hytha, Brookline, MA (US);
Robert John Stephenson, Newton Upper Falls, MA (US);
Samed Halilov, Waltham, MA (US);
Xiangyang Huang, Waltham, MA (US);
Ilija Dukovski, Newtonville, MA (US);
Jean Augustin Chan Sow Fook Yiptong, Worchester, MA (US);
Robert J. Mears, Wellesley, MA (US);
Marek Hytha, Brookline, MA (US);
Robert John Stephenson, Newton Upper Falls, MA (US);
MEARS Technologies, Inc., Waltham, MA (US);
Abstract
A method for making an electronic device may include forming a poled superlattice comprising a plurality of stacked groups of layers and having a net electrical dipole moment. Each group of layers of the poled superlattice may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include coupling at least one electrode to the poled superlattice.