The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2009
Filed:
Mar. 19, 2007
Young-sam Park, Suwon-si, KR;
Seung-beom Yoon, Suwon-si, KR;
Jeong-uk Han, Suwon-si, KR;
Sung-taeg Kang, Seoul, KR;
Seung-jin Yang, Seoul, KR;
Young-Sam Park, Suwon-si, KR;
Seung-Beom Yoon, Suwon-si, KR;
Jeong-Uk Han, Suwon-si, KR;
Sung-Taeg Kang, Seoul, KR;
Seung-Jin Yang, Seoul, KR;
Samsung Electronics Co., Ltd, Suwon-Si, KR;
Abstract
A stack-type nonvolatile semiconductor device comprises a memory device formed on a substrate including a semiconductor body elongated in one direction, having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region on the semiconductor body along the circumference, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate on the semiconductor body, an inter-insulating layer on the memory device, and a conductive layer on the inter-insulating layer, and a memory device formed on the conductive layer including, a semiconductor body elongated in one direction having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region along the circumference of the semiconductor body, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, electrically insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate.